The present invention relates to memory array testing, and more particularly to a system and method for quickly loading test patterns into a memory array.
Many kinds of chips include memory on the chip. Prior to shipping these chips, this memory needs to be tested. Typically, each memory cell is programmed with a first data bit (e.g. a logic xe2x80x9c1xe2x80x9d value), then that data bit is read from the memory cell, then each memory cell is programmed with the opposite data bit (e.g. a logic xe2x80x9c0xe2x80x9d value), and then that data bit is read. In this way, the ability of each cell in the memory array to store logic xe2x80x9c1xe2x80x9d values and logic xe2x80x9c0xe2x80x9d values is verified.
There are several common test patterns that are typically used to test memory arrays. A test pattern is a particular sequence of logic xe2x80x9c1xe2x80x9d values and logic xe2x80x9c0xe2x80x9d values. For example, a checkerboard test pattern for an 8xc3x978 memory array would have alternating logic xe2x80x9c1xe2x80x9d values and logic xe2x80x9c0xe2x80x9d values, for example, as shown in Table 1:
Conventionally, the data for this checkerboard pattern is programmed into a row of a memory array after being serially shifted into a bitline shift register. Memory arrays may be quite large, for example, 4096 rows and columns of memory cells supported by a 4096 latch bitline shift register. For a 4096 cell memory array, this conventional programming method requires 4096 data shifts to load the bitline shift register before each row of the memory array may be loaded. This lengthy delay in loading each row of a test pattern is repeated for each row of the memory array, adding undesirable delay in the memory testing process.
FIG. 1 is a block diagram of a conventional memory system 100. Memory system 100 includes a four-latch bitline shift register 110 and a 4xc3x973 cell memory array 120. Bitline shift register 110 includes a bitline latch L0, a bitline latch L1, a bitline latch L2, and a bitline latch L3. Data QIN applied to bitline shift register 110 is serially shifted through bitline latches L0-L3. When bitline latches L0-L3 store appropriate data, that data is stored in a row of memory array 120. Memory array 120 includes three rows of memory cells, each row controlled by one of row lines RL0-RL2. Each row of memory cells includes four memory cells. For example, row 1 of memory array 120, which is controlled by row line RL1, includes memory cells M10, M11, M12, and M13.
A checkerboard test pattern is conventionally applied to memory array 120 in the following manner. A logic xe2x80x9c0xe2x80x9d value is applied to bitline shift register 110 and shifted into bitline latch L0 as data Q0. A logic xe2x80x9c1xe2x80x9d value is then applied to bitline shift register 110. When the logic xe2x80x9c1xe2x80x9d value is shifted into bitline latch L0 as data Q0, the former logic xe2x80x9c0xe2x80x9d value of data Q0 is shifted into bitline latch L1 as data Q1. Next, a logic xe2x80x9c0xe2x80x9d value is applied to bitline shift register 110. When the logic xe2x80x9c0xe2x80x9d value is shifted into bitline latch L0 as data Q0, the former logic xe2x80x9c1xe2x80x9d value of data Q0 is shifted into bitline latch L1 as data Q1 and the former logic xe2x80x9c0xe2x80x9d value of data Q1 is shifted into bitline latch L2 as data Q2. Again, a logic xe2x80x9c1xe2x80x9d value is applied to bitline shift register 110. When the logic xe2x80x9c1xe2x80x9d value is shifted into bitline latch L0 as data Q0, the former logic xe2x80x9c0xe2x80x9d value of data Q0 is shifted into bitline latch L1 as data Q1, the former logic xe2x80x9c1xe2x80x9d value of data Q1 is shifted into bitline latch L2 as data Q2, and the former logic xe2x80x9c0xe2x80x9d value of data Q2 is shifted into bitline latch L3 as data Q3. As a result, bitline shift register 110 stores a data pattern of xe2x80x9c1, 0, 1, 0xe2x80x9d, as data Q0, Q1, Q2, and Q3. Row line RL2 is enabled to write this data into memory cells M20, M21, M22, and M23, respectively.
As described above, four clock cycles are required to load four-latch bitline shift register 110 with a row of data for a checkerboard pattern prior to storing that data in a row of memory array 120. Shift register 110 must then be loaded with the inverse pattern (e.g., a data pattern of xe2x80x9c0, 1, 0, 1xe2x80x9d as data Q0, Q1, Q2, and Q3), taking another four clock cycles. This new data pattern is written into memory cells M10, M11, M12, and M13, respectively, by enabling row line RL1. Then the original pattern is re-loaded into bitline shift register 110 and store in memory cells M00, M01, M02, and M03. As a result, in addition to the clock cycles required to load each row of memory array 120, twelve clock cycles are needed to load bitline shift register 110. Considering a typical memory array of 4096 memory cells per row, the time required to load memory array 120 becomes a very time-consuming process.
It would be desirable to store rows of test pattern data in bitline shift register 110 in one shot to reduce the delays occurring during memory arrays testing.
Accordingly, a system for testing a memory array is described that allows common memory test patterns to be loaded into a bitline shift register in one shot. In one embodiment of the present invention, a one-shot circuit including a pull-up transistor and a pull-down transistor is added to each bitline latch in the bitline shift register. The desired test pattern may be defined in software, which defines the pull-up and pull-down characteristics of the one-shot circuit for each bitline latch. During normal operation, the one-shot circuit does not affect the serial shifting of data through the bitline shift register. However, during loading of programmed memory test pattern data, the one-shot circuit allows all bitline latches within the bitline shift register to be loaded in parallel. This parallel loading of the bitline latches requires only one clock cycle, as opposed to N clock cycles for conventionally shifting a test pattern into an N-latch-wide conventional bitline shift register. For an N-row memory array, this time savings occurs for every row loaded with one-shot stored data. Consequently, the time required to load each row of the memory array is dramatically decreased.
The present invention will be more fully understood in view of the following description and drawings.